import vs `include in SystemVerilog The compiler goes through a pre-processor step. This step processes all the include files, conditionals, and text macros into a single stream of text. Except for error reporting and debugging, the compiler does not care how many files were used to make up that stream of text. `include directive is just a mechanism for assembling text. The directive provides two key pieces of functionality: Maintain repetitive blocks of text in a single file, Specify file compilation order dependences from within a file instead of on the compiler command line, SystemVerilog also supports separate compilation units. A compilation unit is one stream of text. If you have multiple compiler command lines, then you will have at least one compilation unit per command line. If you have multiple compilation units and have a set of classes that need to be shared across the compilation units, then you must use a package to define those classes or any user defined type. And...